1. Field of the Invention
The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly to a method for forming a capacitor of a semiconductor device, which can suppress formation of bridges between lower electrodes of the capacitor, and can improve various characteristics of the capacitor, in relation to leakage current, capacitance, and breakdown voltage of the capacitor.
2. Description of the Prior Art
As generally known in the art, Dynamic RAMS (DRAMs) store data without being directly and constantly connected to power source, and so they should be refreshed at regular intervals. In other words, DRAMs store data in the form of charge on capacitors, and so require that the capacitors be recharged regularly: every few milliseconds. Further, the larger the capacitance of the capacitors is, the longer the data stored in the DRAMs can be maintained.
However, a recent trend toward a higher integration of semiconductor devices induces reduction in the cell size, accompanied by reduction in the area of capacitors, which results in reduction in capacitance of the capacitors. Therefore, the conventional capacitor construction has difficulties in enabling the capacitors to retain necessary capacitance for maintenance of constant device operation characteristics.
Therefore, various types of highly integrated devices are currently mass-produced, such as devices having lower electrodes (i.e., charge storage electrodes) of various three-dimensional structures in order to increase the surface area, devices having a dielectric layer made from material having a high dielectric constant, or devices having as thin a dielectric layer as possible, in order to secure more than a certain amount of capacitance necessary for cell operation. Such mechanical features of the devices as described are based on a principle that a capacitance of a capacitor is proportional to either a surface area of an electrode or a dielectric constant of a dielectric layer, and is inversely proportional to a spacing between the lower and upper electrodes, i.e., a thickness of the dielectric layer.
Specifically, first, in order to secure a necessary capacitance, the thickness of the dielectric layer or the spacing between the upper and lower electrodes may be reduced. For example, an ONO film lamination (oxide film/nitride film/oxide film) intends to increase a capacitance through reduction in the thickness of the dielectric layer. Second, the dielectric layer may be made from material having a high dielectric constant in order to increase the capacitance. For example, dielectric films of Ta2O2, TaON, and Al2O3 intend to increase a capacitance by employing a dielectric layer made from material having a high dielectric constant. Third, various three dimensional structures of the lower electrodes, such as cylindrical structures, concave structures, and pin-shaped structures, intend to increase a capacitance by increasing the surface area of the electrodes. For example, U.S. Pat. No. 5,655,536 discloses a crown-shaped stacked capacitor, and U.S. Pat. No. 5,716,884 discloses a stacked capacitor having a fin-shaped electrode. In contrast, U.S. Pat. No. 5,877,052 discloses a method of increasing a capacitance of a capacitor by forming hemispherical silicon grains on surfaces of lower electrodes.
Here, in the method of forming the lower electrodes with the hemispherical silicon grains grown on the surfaces of the lower electrodes, silicon grains are deposited and heat-treated on the surfaces of the lower electrodes, so as to cause the surfaces of the lower electrodes to be flexural, thereby increasing the surface area of the lower electrodes and securing the necessary capacitance. The step of forming the hemispherical silicon grains is also called a “meta-stable polysilicon (MPS) process.” When the MPS process has been performed to cause the surfaces of the lower electrodes to be flexural, thereby increasing the surface area of the lower electrodes, the capacitance can be increased up to a value about twice larger than that of a capacitor having flat electrodes. However, the capacitor having flexural electrodes shows an inferior characteristic in relation to current leakage and has a limitation in that a film having excellent step coverage have to be inevitably used as a dielectric layer in the following step.
FIGS. 1a through 1f are cross-sectional views showing a process of forming a conventional capacitor, which will be described hereinafter.
In the step as shown in FIG. 1a, a semiconductor substrate 11 on which an insulating interlayer 12 having plugs 13 is formed is firstly arranged. Then, an etch stop layer 14, an oxide layer 15, and a hard mask layer 16 are deposited in sequence on the insulating interlayer 12.
In the step as shown in FIG. 1b, a photoresist film is applied on the hard mask layer 16 and is then exposed to light and developed, so as to form a photoresist pattern defining a region in which lower electrodes shall be formed. Thereafter, the hard mask layer and the oxide layer 15 are etched while using the photoresist pattern as an etching barrier, so as to form contact holes 17 through which the etch stop layer 14 is exposed. Thereafter, the photoresist pattern and the hard mask layer are eliminated in sequence.
In the step as shown in FIG. 1c, polymers generated when the contact holes 17 are formed are eliminated, and the insides of the contact holes 17 are cleaned so as to increase an effective surface area of the region in which the lower electrodes shall be formed. Here, diluted hydrogen fluoride (DHF) solution or buffered oxide etchant (BOE) solution is used in the cleaning. Thereafter, portions of the etch stop layer 14 under the contact holes 17 are eliminated, so as to expose the plugs 13.
In the step as shown in FIG. 1d, a double polysilicon layer 18 used to form the lower electrodes is deposited on the exposed surfaces of the oxide layer 15 and the inside surfaces of the contact holes 17. Herein, the double polysilicon layer 18 has a dual structure including a doped polysilicon layer 18a and an undoped polysilicon layer 18b. 
In the step as shown in FIG. 1e, another photoresist film is applied to fill the contact holes in which the double polysilicon layer 18 for the lower electrodes is formed. Then, the photoresist film is etched back or subjected to a chemical mechanical polishing (CMP), so as to divide the double polysilicon layer 18 into a plurality of adjacent polysilicon layer segments for the lower electrodes. Thereafter, the photoresist film is eliminated through a stripping process, and the resultant lamination on the substrate is then cleaned.
In the step as shown in FIG. 1f, the hemispherical silicon grains 19 are developed on surfaces of the segments of the undoped polysilicon layer 18b, so as to form the lower electrodes.
Thereafter, although not shown, a dielectric film and an upper electrode are formed in sequence on the lower electrodes having the hemispherical silicon grains 19 formed on the surfaces thereof, thereby completing a capacitor.
However, such a conventional method for forming a capacitor of a semiconductor device as described above has several problems as follows.
FIG. 2a is a photograph showing the contact holes which are in a state after being cleaned after being formed by etching an oxide layer. The cleaning is performed in order to increase the effective surface area of the region in which the lower electrodes shall be formed and eliminate the polymers remaining after the etching. However, FIG. 2a shows a capacitor in which the oxide layer is insufficiently etched and remains at lower portions of the contact holes, thereby failing to achieve actual increase in the effective surface area of the region in which the lower electrodes shall be formed. Herein, when a quantity of the etched oxide layer is increased, the space between cells may become insufficient and bridges may be formed between cells. In contrast, it is nearly impossible to increase the capacitance of the capacitor when the etching is carried out in such a degree as to prevent bridges from being formed between cells.
FIGS. 2b and 2c are photographs of a lamination formed on a substrate, including hemispherical silicon grains developed thereon, taken from above and side of the lamination.
In partially eliminating the polysilicon layer for the lower electrodes deposited on the oxide layer in order to form the electrically separated lower electrodes, a photoresist film is applied to fill the contact holes, and then, the photoresist film is etched back to eliminate the polysilicon layer for the lower electrodes deposited on the oxide layer.
Here, the difference between the etching rates of the oxide layer and the polysilicon layer for the lower electrodes may cause loss of an upper portion of the oxide layer, which causes the polysilicon layer segments for the lower electrodes to protrude outward beyond the oxide layer. As a result, the excessively protruding polysilicon layer segments for the lower electrodes may induce excessive development of hemispherical silicon grains, and may induce formation of hemispherical silicon grains even on outer wall surfaces of the lower electrodes.
FIG. 2d illustrates graphs showing diffusion of phosphorus P from the doped polysilicon layer to the undoped polysilicon layer when the lamination has been subjected to an annealing at 650° C. in order to grow the hemispherical silicon grains on the undoped polysilicon layer. Here, a doped polysilicon layer having a thickness of 300 Å and an undoped polysilicon layer having a thickness of 100 Å and doped with phosphorus at a density of 24E20 atoms/cc were employed in the experiment as shown in the graphs of FIG. 2d. 
As a result of the annealing, the entire doping profile shows no change, but it is noted that the diffusion of the phosphorus has lowered the doping density at the surface of the doped polysilicon layer down to 1E19˜1E18 atoms/cc.
As described above, in order to increase growth of hemispherical silicon grains, the undoped silicon for the lower electrodes is deposited with an increased thickness, and the hemispherical silicon grains are grown on the undoped silicon layer. Then, the hemispherical silicon grains are excessively grown and phosphorus is diffused in the doped polysilicon layer, thereby causing a thinning phenomenon, in which the thickness of the doped polysilicon layer is reduced. As a result, pinholes are formed in the doped polysilicon layer, and cleaning solution may come into the pinholes and etch the oxide layer, thereby forming holes in the oxide layer, in the following cleaning step. Consequently, in the following step of depositing the dielectric film, the dielectric film may be deposited in the entire holes so as to form bridges between cells.
FIG. 2e is a photograph showing pinholes formed in the doped polysilicon layer according to the thinning phenomenon, that is, reduction of the thickness of the doped polysilicon layer.
Here, the pinholes formed while the hemispherical silicon grains are grown degrade various characteristics of the capacitor, in relation to leakage current, capacitance, and breakdown voltage of the capacitor.